1. Field of the Invention
The present invention relates to an apparatus and method for planarization of a material, such as a metal, on a substrate.
2. Background of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and now electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or xe2x80x9cpolishingxe2x80x9d a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, typically a slurry or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition, or slurry, to effect chemical activity and/or mechanical activity and consequential removal of material from the surface of the substrate.
Copper is becoming a metal of choice in ULSI to form interconnects that provide the conductive pathway in integrated circuits and other electronic devices. Copper is a material having advantageous properties such as lower resistance and better electromigration performance compared to traditional materials such as aluminum. Copper can be deposited by various techniques such as PVD, CVD and electroplating. Electroplating (ECP) is seen as a low cost and effective deposition technique with promise. ECP is performed by introducing a substrate into a plating bath and applying a current to the substrate. The copper ions plate out of solution and deposit onto the substrate.
However, copper is difficult to pattern and etch. Accordingly, copper features are formed using damascene or dual damascene processes. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. A barrier layer is deposited conformally on the surfaces of the features formed in the dielectric layer prior to deposition of the copper. Copper is then deposited over the barrier layer and the surrounding field. The copper deposited on the field is removed by CMP processes to leave the copper filled feature formed in the dielectric material. Both abrasive and abrasive free CMP processes are available and others are being developed to remove copper. Abrasives refer to particulate material, such as alumina or silica, added to the polishing slurry or released from a fixed-abrasive polishing pad during polishing which provide mechanical abrasion to a substrate surface being polished.
Additionally, substrate surfaces may have different surface topography, depending on the density or size of features formed therein, which makes effective conformal removal of copper material from the substrate surface difficult to achieve. For example, it has been observed that copper material is removed from a dense feature area of the substrate surface at a slower removal rate as compared to removing copper material from a substrate surface area having few, if any, features formed therein. Additionally, the relatively uneven removal rates can result in underpolishing of areas of the substrate with residual copper material remaining after the polishing process.
One solution to removing all of the desired copper material from the substrate surface is overpolishing the substrate surface. However, overpolishing of some materials can result in the formation of topographical defects, such as concavities or depressions in features, referred to as dishing, or excessive removal of dielectric material, referred to as erosion. The topographical defects from dishing and erosion can further lead to non-uniform removal of additional materials, such as barrier layer materials disposed thereunder, and produce a substrate surface having a less than desirable polishing quality.
Another problem with the polishing of copper surfaces arises from the use of low dielectric constant (low k) dielectric materials to form copper damascenes in the substrate surface. Low k dielectric materials, such as carbon doped silicon oxides, may deform or scratch under conventional polishing pressures (i.e., about 6 psi), called downforce, which can detrimentally affect substrate polish quality and detrimentally affect device formation. For example, rotational relative movement between the substrate and a polishing pad can induce a shear force along the substrate surface and deform the low k material to form topographical defects, such as scratches, which can detrimentally affect subsequent polishing.
As a result, there is a need for an apparatus and method for depositing and planarizing a metal layer, such as a copper layer, on a substrate.
Aspects of the invention generally provide methods and apparatus for planarizing a substrate surface with reduced contact pressure between a substrate and a polishing apparatus. In one aspect, a method is provided for processing a substrate including positioning the substrate in an electrolyte solution comprising a corrosion inhibitor, forming a passivation layer on a substrate surface, polishing the substrate in the electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface.
In another aspect, a method is provided for processing a substrate including positioning the substrate in an electrolyte solution adjacent polishing article, the electrolyte including a corrosion inhibitor, a leveling agent, a viscous forming agent, or combinations thereof, to form a current suppressing layer on a substrate surface, polishing the substrate in the electrolyte solution with the polishing article to remove at least a portion of the current suppressing layer, applying a bias between an anode and a cathode disposed in the electrolyte solution, and removing material from at least a portion of the substrate surface with anodic dissolution.
In another aspect, an apparatus is provided for processing substrates including a partial enclosure defining a processing region and having a fluid inlet and a fluid outlet, an cathode disposed in the partial enclosure, polishing article disposed in the partial enclosure, a substrate carrier movably disposed above the polishing article, the substrate carrier having a substrate mounting surface, a power source connected to at least the partial enclosure, and a computer based controller configured to cause the apparatus to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.
In another aspect, an electrochemical deposition system is provided that includes a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more electrochemical processing cells disposed in connection with the mainframe, one or more polishing platens disposed in connection with the mainframe, an electrolyte supply fluidly connected to the one or more electrochemical processing cells, and one or more polishing fluid supplies connected to the one or more.